SH7059 Datasheet, PDF (184/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Interrupt Controller (INTC)
7.5 Interrupt Response Time
Table 7.5 indicates the interrupt response time, which is the time from the occurrence of an interrupt request until the
interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. Figure 7.4
shows an example of pipeline operation when an IRQ interrupt is accepted.
Table 7.5 Interrupt Response Time
Number of States
Item
Peripheral Module NMI
IRQ
Notes
Synchronizing input signal
(synchronized with
peripheral clock Pφ) with
internal clock φ and DMAC
activation judgment
0 or 6
1 to 4
6 to 9
For the number of states
required for each interrupt,
see the note below.
Compare identified interrupt 2
2
2
priority with SR mask level
Wait for completion of
sequence currently being
executed by CPU
X (≥ 0)
The longest sequence is for
interrupt or address-error
exception processing (X = 4
+ m1 + m2 + m3 + m4). If
an interrupt-masking
instruction follows, however,
the time may be even
longer.
Time from start of interrupt
exception processing until
fetch of first instruction of
exception service routine
starts
5 + m1 + m2 + m3
Performs the PC and SR
saves and vector address
fetch.
Interrupt
response time
Total: (7 or 13)
(8 or 11)
(13 to 16)
+ m1 + m2 + m3 + X + m1 + m2 + m3 + X + m1 + m2 + m3 + X
Minimum: 10
11
16
Maximum: 17 + 2
(m1 + m2 + m3) +
m4
15 + 2
20 + 2
(m1 + m2 + m3) + m4 (m1 + m2 + m3) + m4
Notes: When m1 = m2 = m3 = m4 = 1
m1–m4 are the number of states needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
* Number of states needed for synchronization and DMAC activation judgment
The relations between numbers of states needed for synchronizing an input signal (synchronized with the
peripheral clock Pφ) with the internal clock φ and DMAC activation judgment and vector numbers are shown
below.
0 state: 9, 10, 12, 13, 14, 72, 74, 76, 78, 189, 193, and 224
6 states: Peripheral module interrupts other than vector number 222 (HCAN0/RM0) and the above.
7 states: Interrupts with vector number 222 requested by HCAN0 Mailbox 0 (the needed states for this interrupt
differs from other interrupts with vector number 222 since the interrupt by HCAN0 Mailbox 0 can activate the
DMAC.)
6 states: Interrupts with vector number 222 other than the above
The same number of states is needed to cancel interrupt sources.
Rev.3.00 Mar. 12, 2008 Page 94 of 948
REJ09B0177-0300