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SH7059 Datasheet, PDF (932/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer
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29. Electrical Characteristics
CK
(input)
(output)
,,
,
A21–A0,
D15–D0
VOH
tBRQS
VOH
VOL
tBACKD1
VOL
tBZD
Hi-Z
tBZD
Hi-Z
VOH
tBRQS
VOL
VIH
tBACKD2
VOH
Figure 29.8 Bus Right Release Timing
29.3.4 Bus Timing
Table 29.9 shows bus timing.
Table 29.9 Bus Timing
Conditions: VCC = PLLVCC = 3.3 V ±0.3 V, PVCC1 = 3.3 V ±0.3 V,
PVCC2 = 5.0 V ±0.5 V, AVCC = 5.0 V ±0.5 V, AVref = 4.5 V to AVCC,
VSS = PLLVSS = AVSS = 0 V, Ta = –40°C to 125°C.
When PVCC1 = 3.3 V ±0.3 V, VCC = PVCC1.
When writing or erasing on-chip flash memory, Ta = –40°C to 85°C.
Item
Symbol
Min
Max
Unit
Address delay time
tAD
—
35
ns
CS delay time 1
tCSD1
—
30
ns
CS delay time 2
t
—
CSD2
30
ns
Read strobe delay time 1
tRSD1
—
30
ns
Read strobe delay time 2
tRSD2
—
30
ns
Read data setup time
tRDS
15
—
ns
Read data hold time
tRDH
0
—
ns
Write strobe delay time 1
tWSD1
—
30
ns
Write strobe delay time 2
tWSD2
—
30
ns
Write data delay time
tWDD
—
30
ns
Write data hold time
tWDH
tcyc × m
—
ns
WAIT setup time
tWTS
15
—
ns
WAIT hold time
tWTH
0
—
ns
Read data access time
tACC
tcyc × (n+1.5)-39 —
ns
Access time from read strobe tOE
tcyc × (n+1.0)-39 —
ns
Write address setup time
tAS
0
—
ns
Write address hold time
tWR
5
—
ns
Legend:
n: Number of waits
m = 1: CS assertion extension cycle
m = 0: Normal cycle (CS assertion non-extension cycle)
Rev.3.00 Mar. 12, 2008 Page 842 of 948
REJ09B0177-0300
Figures
Figures 29.9,
29.10
Figure 29.11
Figures 29.9,
29.10
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