SH7059 Datasheet, PDF (553/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Controller Area Network-II (HCAN-II)
17.6.1 Timer Counter Register n (TCNTRn) (n = 0, 1)
The timer counter register (TCNTR) is a 16-bit readable/writable register that allows the CPU to monitor and modify the
value of the free-running timer counter. When the timer matches TCMR0 (timer compare match register 0) and TCR11 is
set to 1, TCNTR is set to LOSR (local offset register) and counting starts again.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCNTR[15:0]
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Bit
Bit Name Initial Value R/W Description
15 to 0 TCNTR[15:0] 0
R/W* Indicate the value of the free-running timer.
Note: * This register is cleared by the compare match condition.
17.6.2 Timer Control Register_n (TCR_n) (n = 0, 1)
The timer control register (TCR) is a 16-bit readable/writable register that controls the operation of the timer. This register
should be set before each periodical transmission or the deadline monitor register is set and the timer operation starts.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCR TCR TCR TCR TCR TCR TCR9
15 14 13 12 11 10
TCR7
TCR5 TCR4 TCR3 TCR2 TCR1 TCR0
Initial Value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W ⎯ R/W ⎯ R/W R/W R/W R/W R/W R/W
Bit
Bit Name Initial Value R/W Description
15
TCR15
0
R/W Enable Timer
When this bit is set, the timer runs. When this bit is cleared, the timer
completes the current cycle (notified by timer overrun or a compare match
condition on TCMR0) and is cleared to 0.
0: Timer stops running and is cleared at the end of current cycle
1: Timer is running
Important: There is a failure on the timer function in the SH7059. This bit
must be written to 0 not to activate the timer.
14
TCR14
0
R/W Disable ICR0
Enables or disables the input capture register 0 (ICR0). When this bit is
enabled, the timer value is always captured every time a start of frame
(SOF) is output to the CAN bus, whether the HCAN is a transmitter or
receiver. When this bit is disabled, the value of ICR0 remains latched.
0: ICR0 is disabled and holds the current value
Clearing condition:TCR9 = 1 when CAN-ID of receive message is equal to
the ID of a mailbox with CCM set
1: ICR0 is enabled and captures the timer value at every SOF
Rev.3.00 Mar. 12, 2008 Page 463 of 948
REJ09B0177-0300