SH7059 Datasheet, PDF (233/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Direct Memory Access Controller (DMAC)
10.3.3 Channel Priority
When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to the
following priority order:
• CH0 > CH1 > CH2 > CH3
10.3.4 DMA Transfer Types
The DMAC supports the transfers shown in table 10.3. It operates in dual address mode, in which both the transfer source
and destination addresses are output. The dual address mode consists of a direct address mode, in which the output address
value is the object of a direct data transfer, and an indirect address mode, in which the output address value is not the
object of the data transfer, but the value stored at the output address becomes the transfer object address. The actual
transfer operation timing varies with the bus mode. The DMAC has two bus modes: cycle-steal mode and burst mode.
Table 10.3 Supported DMA Transfers
Transfer
Destination
Transfer Source
Memory-Mapped
External Memory External Device
External memory
Supported
Supported
Memory-mapped external Supported
device
Supported
On-chip memory
Supported
Supported
On-chip peripheral module Supported
Supported
On-Chip Memory
Supported
Supported
On-Chip Peripheral
Module
Supported
Supported
Supported
Supported
Supported
Supported
Rev.3.00 Mar. 12, 2008 Page 143 of 948
REJ09B0177-0300