SH7059 Datasheet, PDF (40/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Differences between SH7058 and SH7058S/SH7059
SH7058 (Rev.3, REJ09B0046-0300H)
22.5.2 Port D Data Register (PDDR)
811
PDDR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode
or sleep mode.
22.6.1 Register Configuration
Table 22.9 Register Configuration
813
Note: Register access with an internal clock multiplication
ratio of 4 requires four or five internal clock (φ) cycles.
22.6.2 Port E Data Register (PEDR)
814
PEDR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode
or sleep mode.
22.7 Port F
Figure 22.6 Port F
816
Single-chip mode
PF15 (I/O)
PF14 (I/O)
SH7058S/SH7059
23.5.2 Port D Data Register (PDDR)
Description amended
PDDR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), in hardware standby
mode, and in software standby mode. It is not initialized in
sleep mode.
23.6.1 Register Configuration
Table 23.9 Register Configuration
Note deleted
23.6.2 Port E Data Register (PEDR)
Description amended
PEDR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), in hardware standby
mode, and in software standby mode. It is not initialized in
sleep mode.
23.7 Port F
Figure 23.6 Port F
Figure amended
Single-chip mode
PF15 (I/O) / SCS1 (I/O)
PF14 (I/O) / SCS0 (I/O)
22.7.1 Register Configuration
Table 22.11 Register Configuration
816
Note: Register access with an internal clock multiplication
ratio of 4 requires four or five internal clock (φ) cycles.
22.7.2 Port F Data Register (PFDR)
817
Bits PF15DR to PF0DR correspond to pins PF15/BREQ to
PF0/A16.
… PFDR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode
or sleep mode.
22.8.1 Register Configuration
Table 22.13 Register Configuration
819
Note: Register access with an internal clock multiplication
ratio of 4 requires four or five internal clock (φ) cycles.
22.8.2 Port G Data Register (PGDR)
819
PGDR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode
or sleep mode.
23.7.1 Register Configuration
Table 23.11 Register Configuration
Note deleted
23.7.2 Port F Data Register (PFDR)
Description amended
Bits PF15DR to PF0DR correspond to pins
PF15/BREQ/SCS1 to PF0/A16.
… PFDR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), in hardware standby
mode, and in software standby mode. It is not initialized in
sleep mode.
23.8.1 Register Configuration
Table 23.13 Register Configuration
Note deleted
23.8.2 Port G Data Register (PGDR)
Description amended
PGDR is initialized to H'0000 by a power-on reset
(excluding a WDT power-on reset), in hardware standby
mode, and in software standby mode. It is not initialized in
sleep mode.
Rev.3.00 Mar. 12, 2008 Page xl of xc
REJ09B0177-0300