SH7059 Datasheet, PDF (200/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Bus State Controller (BSC)
9.1.2 Block Diagram
Figure 9.1 shows the BSC block diagram.
On-chip
memory
control unit
WAIT
Wait
control unit
RAMER
Bus interface
WCR
CS0–CS3
Area
control unit
BCR1
BCR2
RD
WRH, WRL
Memory
control unit
BREQ
BACK
Bus
arbitration
control unit
BSC
Legend:
WCR: Wait control register
RAMER: RAM emulation register
BCR1:
BCR2:
Bus control register 1
Bus control register 2
Figure 9.1 BSC Block Diagram
Rev.3.00 Mar. 12, 2008 Page 110 of 948
REJ09B0177-0300