SH7059 Datasheet, PDF (436/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Compare Match Timer (CMT)
14.1.3 Register Configuration
Table 14.1 summarizes the CMT register configuration.
Table 14.1 Register Configuration
Channel Name
Abbreviation R/W
Initial Value Address
Shared
Compare match timer startCMSTR
register
R/W
H'0000
H'FFFFF710
0
Compare match timer CMCSR0
R/(W)* H'0000
H'FFFFF712
control/status register 0
Compare match timer
counter 0
CMCNT0
R/W
H'0000
H'FFFFF714
Compare match timer
constant register 0
CMCOR0
R/W
H'FFFF
H'FFFFF716
1
Compare match timer CMCSR1
R/(W)* H'0000
H'FFFFF718
control/status register 1
Compare match timer
counter 1
CMCNT1
R/W
H'0000
H'FFFFF71A
Compare match timer
constant register 1
CMCOR1
R/W
H'FFFF
H'FFFFF71C
Note: * Only 0 can be written to the CMCSR0 and CMCSR1 CMF bits to clear the flags.
Access Size (Bits)
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
14.2 Register Descriptions
14.2.1 Compare Match Timer Start Register (CMSTR)
The compare match timer start register (CMSTR) is a 16-bit register that selects whether to operate or halt the channel 0
and channel 1 counters (CMCNT). It is initialized to H'0000 by a power-on reset and in the standby modes.
Bit:
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
–
–
–
–
–
–
STR1
STR0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R/W
R/W
• Bits 15–2—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 1—Count Start 1 (STR1): Selects whether to operate or halt compare match timer counter 1.
Bit 1: STR1
0
1
Description
CMCNT1 count operation halted
CMCNT1 count operation
(Initial value)
Rev.3.00 Mar. 12, 2008 Page 346 of 948
REJ09B0177-0300