SH7059 Datasheet, PDF (452/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Serial Communication Interface (SCI)
• Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and enable or disable clock
output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock
output, or serial clock input. Select the SCK pin function by using the pin function controller (PFC).
The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally clocked (CKE1 = 0). The
CKE0 setting is ignored in synchronous mode, or when an external clock source is selected (CKE1 = 1). For further
details on selection of the SCI clock source, see table 15.9 in section 15.3, Operation.
Bit 1: CKE1 Bit 0: CKE0 Description*¹
0
0
Asynchronous mode Internal clock, SCK pin used for input pin (input signal is
ignored) or output pin (output level is undefined)*²
Synchronous mode Internal clock, SCK pin used for synchronous clock output*²
0
1
Asynchronous mode Internal clock, SCK pin used for clock output*³
Synchronous mode Internal clock, SCK pin used for synchronous clock output
1
0
Asynchronous mode External clock, SCK pin used for clock input*⁴
Synchronous mode External clock, SCK pin used for synchronous clock input
1
1
Asynchronous mode External clock, SCK pin used for clock input*⁴
Synchronous mode External clock, SCK pin used for synchronous clock input
Notes: 1. The SCK pin is multiplexed with other functions. Use the pin function controller (PFC) to select the SCK function
for this pin, as well as the I/O direction.
2. Initial value.
3. The output clock frequency is the same as the bit rate.
4. The input clock frequency is 16 times the bit rate.
15.2.7 Serial Status Register (SSR)
Bit:
7
6
5
TDRE
RDRF
ORER
Initial value:
1
0
0
R/W: R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written to clear the flag.
4
FER
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate the
SCI operating status.
The CPU can always read and write to SSR, but cannot write 1 in the status flags (TDRE, RDRF, ORER, PER, and FER).
These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 2 (TEND) and 1 (MPB) are
read-only bits that cannot be written. SSR is initialized to H'84 by a power-on reset, and in hardware standby mode and
software standby mode. It is not initialized by a manual reset.
Rev.3.00 Mar. 12, 2008 Page 362 of 948
REJ09B0177-0300