SH7059 Datasheet, PDF (133/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. CPU
Table 2.13 Arithmetic Operation Instructions
Instruction
ADD
Rm,Rn
ADD
#imm,Rn
ADDC Rm,Rn
ADDV Rm,Rn
CMP/EQ #imm,R0
CMP/EQ Rm,Rn
CMP/HS Rm,Rn
CMP/GE Rm,Rn
CMP/HI Rm,Rn
Instruction Code
0011nnnnmmmm1100
0111nnnniiiiiiii
0011nnnnmmmm1110
0011nnnnmmmm1111
10001000iiiiiiii
0011nnnnmmmm0000
0011nnnnmmmm0010
0011nnnnmmmm0011
0011nnnnmmmm0110
CMP/GT Rm,Rn
CMP/PL Rn
CMP/PZ Rn
CMP/STR Rm,Rn
0011nnnnmmmm0111
0100nnnn00010101
0100nnnn00010001
0010nnnnmmmm1100
DIV1 Rm,Rn
0011nnnnmmmm0100
DIV0S Rm,Rn
0010nnnnmmmm0111
DIV0U
DMULS.L Rm,Rn
0000000000011001
0011nnnnmmmm1101
DMULU.L Rm,Rn
0011nnnnmmmm0101
DT
Rn
0100nnnn00010000
EXTS.B Rm,Rn
0110nnnnmmmm1110
EXTS.W Rm,Rn
0110nnnnmmmm1111
EXTU.B Rm,Rn
0110nnnnmmmm1100
EXTU.W Rm,Rn
0110nnnnmmmm1101
MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
MUL.L Rm,Rn
MULS.W Rm,Rn
0000nnnnmmmm0111
0010nnnnmmmm1111
Operation
Execu-
tion
Cycles T Bit
Rn + Rm → Rn
1
—
Rn + imm → Rn
1
—
Rn + Rm + T → Rn, Carry → T
1
Carry
Rn + Rm → Rn, Overflow → T
1
Overflow
If R0 = imm, 1 → T
1
Comparison result
If Rn = Rm, 1 → T
1
Comparison result
If Rn=Rm with unsigned data, 1 → T
1
Comparison result
If Rn = Rm with signed data, 1 → T
1
Comparison result
If Rn > Rm with
unsigned data, 1 → T
1
Comparison result
If Rn > Rm with signed data, 1 → T
1
Comparison result
If Rn > 0, 1 → T
1
Comparison result
If Rn = 0, 1 → T
1
Comparison result
If Rn and Rm have
an equivalent byte,
1→T
1
Comparison result
Single-step division
(Rn ÷ Rm)
1
Calculation result
MSB of Rn → Q, MSB
of Rm → M, M ^ Q → T
1
Calculation result
0 → M/Q/T
1
0
Signed operation of Rn
2 to 4* —
× Rm → MACH, MACL 32 × 32 → 64 bits
Unsigned operation of Rn × Rm → MACH, 2 to 4* —
MACL 32 × 32 → 64 bits
Rn – 1 → Rn, when Rn is 0, 1 → T. When 1
Rn is nonzero, 0 → T
Comparison result
Byte in Rm is sign-extended → Rn
1
—
Word in Rm is sign-extended → Rn
1
—
Byte in Rm is zero-extended → Rn
1
—
Word in Rm is zero-extended → Rn
1
—
Signed operation of
3/
—
(Rn) × (Rm) + MAC → MAC 32 × 32 + 64 → (2 to 4)*
64 bits
Signed operation of
3/(2)* —
(Rn) × (Rm) + MAC → MAC 16 × 16 + 64 →
64 bits
Rn × Rm → MACL,
32 × 32 → 32 bits
2 to 4* —
Signed operation of
Rn × Rm → MACL 16 ×
16 → 32 bits
1 to 3* —
Rev.3.00 Mar. 12, 2008 Page 43 of 948
REJ09B0177-0300