SH7059 Datasheet, PDF (443/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Serial Communication Interface (SCI)
Section 15 Serial Communication Interface (SCI)
15.1 Overview
This LSI has a serial communication interface (SCI) with five independent channels.
The SCI supports both asynchronous and synchronous serial communication. It also has a multiprocessor communication
function for serial communication between two or more processors, and a clock inverted input/output function.
15.1.1 Features
The SCI has the following features:
• Selection of asynchronous or synchronous as the serial communication mode
⎯ Asynchronous mode
Serial data communication is synchronized in character units. The SCI can communicate with a universal
asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any
other chip that employs standard asynchronous serial communication. It can also communicate with two or more
other processors using the multiprocessor communication function. There are twelve selectable serial data
communication formats.
• Data length: seven or eight bits
• Stop bit length: one or two bits
• Parity: even, odd, or none
• Multiprocessor bit: one or none
• Receive error detection: parity, overrun, and framing errors
• Break detection: by reading the RxD level directly when a framing error occurs
⎯ Synchronous mode
Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having
a synchronous communication function. There is one serial data communication format.
• Data length: eight bits
• Receive error detection: overrun errors
• Serial clock inverted input/output
• Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and
receive simultaneously. Both sections use double buffering, so continuous data transfer is possible in both the transmit
and receive directions.
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: baud rate generator (internal) or SCK pin (external)
• Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are
requested independently. The transmit-data-empty and receive-data-full interrupts can start the direct memory access
controller (DMAC) to transfer data.
• Selection of LSB-first or MSB-first transfer (8-bit length)
This selection is available regardless of the communication mode. (The descriptions in this section are based on LSB-
first transfer.)
Rev.3.00 Mar. 12, 2008 Page 353 of 948
REJ09B0177-0300