SH7059 Datasheet, PDF (161/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6.4 Interrupts
6. Exception Processing
6.4.1 Interrupt Sources
Table 6.7 shows the sources that start up interrupt exception processing. These are divided into NMI, user breaks, H-UDI,
IRQ, and on-chip peripheral modules.
Table 6.7 Interrupt Sources
Type
NMI
User break
H-UDI
IRQ
On-chip peripheral module
Request Source
NMI pin (external input)
User break controller
High-performance user debug interface
IRQ0–IRQ7 (external input)
Direct memory access controller (DMAC)
Advanced timer unit-II (ATU-II)
Compare match timer (CMT)
A/D converter
Serial communication interface (SCI)
Synchronous communication unit (SSU)
Watchdog timer (WDT)
Controller area network-II (HCAN-II)
Number of Sources
1
1
1
8
4
75
2
3
20
6
1
8
Each interrupt source is allocated a different vector number and vector table offset. See table 7.3, Interrupt Exception
Processing Vectors and Priorities, in section 7, Interrupt Controller (INTC), for more information on vector numbers and
vector table address offsets.
6.4.2 Interrupt Priority Level
The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt
controller (INTC) determines their relative priorities and starts up processing according to the results.
The priority order of interrupts is expressed as priority levels 0–16, with priority 0 the lowest and priority 16 the highest.
The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. The user break interrupt and H-UDI
interrupt priority level is 15. IRQ interrupts and on-chip peripheral module interrupt priority levels can be set freely using
the INTC's interrupt priority registers A through L (IPRA to IPRL) as shown in table 6.8. The priority levels that can be
set are 0–15. Level 16 cannot be set. See section 7.3.1, Interrupt Priority Registers A–L (IPRA-IPRL), for details of the
interrupt priority registers.
Table 6.8 Interrupt Priority Order
Type
NMI
User break
H-UDI
IRQ
On-chip peripheral module
Priority Level Comment
16
Fixed priority level. Cannot be masked.
15
Fixed priority level.
15
Fixed priority level.
0–15
Set with interrupt priority level setting registers A through L (IPRA to IPRL).
0–15
Set with interrupt priority level setting registers A through L (IPRA to IPRL).
Rev.3.00 Mar. 12, 2008 Page 71 of 948
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