SH7059 Datasheet, PDF (904/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

27. Power-Down State
Table 27.1 shows the transition conditions for entering the modes from the program execution state, as well as the CPU
and peripheral module status in each mode and the procedures for canceling each mode.
Table 27.1 Power-Down State Conditions
Mode
Hardware
standby
Software
standby
Entering Procedure
Clock
Low-level input at HSTBY Halted
pin
(Power
supply
stopped)
Execute SLEEP instructionHalted
with SSBY
bit set to 1 in SBYCR
(Power
supply
stopped)
CPU
Halted
(Power
supply
stopped)
Halted
(Power
supply
stopped)
State
On-Chip
Peripheral
Modules
RAM
Halted
Held^*1
(Power supply
stopped)
Halted^*1
Held
(Power supply
stopped)
Pins
Initialized
Canceling
Procedure
High-level input at
HSTBY pin,
executing power-
on reset
High
•
impedance^*2
•
Rising edge of
NMI
Power-on
reset
Sleep
Execute SLEEP instructionRuns
with SSBY
bit cleared to 0 in SBYCR
Halted and Runs
held in
registers
Runs
Runs
• Interrupt
• DMA address
error
• Power-on
reset
• Manual reset
Legend:
SBYCR: Standby control register
SSBY: Software standby bit
Notes: 1. Clear the RAME bit in SYSCR1 to 0 in advance when changing the state from the program execution state in
hardware standby mode.
2. When leaving software standby mode, the inside of this LSI is initiated in the reset state. The pin function
controller and I/O port-related registers are initialized. For details on the pin state, see Appendix B, Pin States.
27.1.2 Pin Configuration
Pins related to power-down modes are shown in table 27.2.
Table 27.2 Pin Configuration
Pin Name
Hardware standby input pin
Abbreviation
HSTBY
I/O
Input
Power-on reset input pin
NMI input pin
RES
NMI
Input
Input
Function
Input level determines transition to
hardware standby mode
Power-on reset signal input pin
Input for NMI interrupt and for canceling
software standby mode
Rev.3.00 Mar. 12, 2008 Page 814 of 948
REJ09B0177-0300