SH7059 Datasheet, PDF (179/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

7. Interrupt Controller (INTC)
Table 7.4 Interrupt Request Sources and IPRA–IPRL
Register
Interrupt priority register A
Interrupt priority register B
Interrupt priority register C
Interrupt priority register D
Interrupt priority register E
Interrupt priority register F
Interrupt priority register G
Interrupt priority register H
Interrupt priority register I
Interrupt priority register J
Interrupt priority register K
Interrupt priority register L
15–12
IRQ0
IRQ4
DMAC0, 1
ATU03
ATU13
ATU31
ATU51
ATU81
ATU91
ATU11
SCI0/SSU0*
SCI4
Bits
11–8
7–4
3–0
IRQ1
IRQ2
IRQ3
IRQ5
IRQ6
IRQ7
DMAC2, 3
ATU01
ATU02
ATU04
ATU11
ATU12
ATU21
ATU22
ATU23
ATU32
ATU41
ATU42
ATU52
ATU6
ATU7
ATU82
ATU83
ATU84
ATU92
ATU101
ATU102
CMT0, A/D0, MTAD0 CMT1, A/D1, MTAD1 A/D2
SCI1
SCI2/SSU1*
SCI3
HCAN0
WDT
HCAN1
As indicated in table 7.4, four IRQ pins or groups of 4 on-chip peripheral modules are allocated to each register. Each of
the corresponding interrupt priority ranks are established by setting a value from H'0 (0000) to H'F (1111) in each of the
four-bit groups 15–12, 11–8, 7–4 and 3–0. Interrupt priority rank becomes level 0 (lowest) by setting H'0, and level 15
(highest) by setting H'F. If multiple on-chip peripheral modules are assigned to the same bit (DMAC0 and DMAC1,
DMAC2 and DMAC3, CMT0, A/D0, and MTAD0, CMT1, A/D1, and MTAD1, SCI0 and SSU0*, and SCI2 and SSU1*),
those multiple modules are set to the same priority rank.
IPRA–IPRL are initialized to H'0000 by a reset, in hardware standby mode and in software standby mode.
Note: * SSU: Synchronous Serial Communication Unit
7.3.2 Interrupt Control Register (ICR)
Bit:
15
14
13
12
11
10
9
8
NMIL
—
—
—
—
—
—
NMIE
Initial value:
*
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bit:
7
6
5
4
IRQ0S
IRQ1S
IRQ2S
IRQ3S
Initial value:
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
Note: * When NMI input is high: 1; when NMI input is low: 0
3
IRQ4S
0
R/W
2
IRQ5S
0
R/W
1
IRQ6S
0
R/W
0
IRQ7S
0
R/W
ICR is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and IRQ0 –IRQ7
and indicates the input signal level at the NMI pin. A reset, hardware standby mode, and software standby mode initialize
ICR.
Rev.3.00 Mar. 12, 2008 Page 89 of 948
REJ09B0177-0300