SH7059 Datasheet, PDF (773/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

24. ROM (SH7058S)
H'000000
EB0
H'001000
EB1
H'002000
EB2
H'003000
EB3
H'004000
EB4
H'005000
EB5
H'006000
EB6
H'007000
EB7
H'008000
This area is accessible as both a RAM
area and as a flash memory area.
H'FFFF0000
H'FFFF0FFF
Flash memory
(user MAT)
EB8 to EB15
On-chip RAM
H'0FFFFF
H'FFFFBFFF
Figure 24.18 Example of Overlapped RAM Operation
Figure 24.18 shows an example of an overlap on block area EB0 of the flash memory.
Emulation is possible for a single area selected from among the eight areas, from EB0 to EB7, of the user MAT. The area
is selected by the setting of the RAM2 to RAM0 bits in RAMER.
(1) To overlap a part of the RAM on area EB0, to allow realtime programming of the data for this area, set the RAMS bit
in RAMER to 1, and each of the RAM2 to RAM0 bits to 0.
(2) Realtime programming is carried out using the overlaid area of RAM.
In programming or erasing the user MAT, it is necessary to run a program that implements a series of procedural steps,
including the downloading of an on-chip program. In this process, set the download area with FTDAR so that the overlaid
RAM area and the area where the on-chip program is to be downloaded do not overlap. The initial setting (H'00) of
FTDAR causes the tuned data area to overlap with the download area. When using the initial setting of FTDAR, the data
that is to be programmed must be saved beforehand in an area that is not used by the system.
Figure 24.19 shows an example of programming data that has been emulated to the EB0 area in the user MAT.
Rev.3.00 Mar. 12, 2008 Page 683 of 948
REJ09B0177-0300