SH7059 Datasheet, PDF (409/1042 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Advanced Timer Unit-II (ATU-II)
Contention between Interrupt Status Flag Clearing by DMAC and Setting by Input Capture/Compare-Match: If a
clear request signal is generated by the DMAC when the interrupt status flag (ICF0A to ICF0D, CMF6A to CMF6D,
CMF7A to CMF7D) is set by input capture (ICR0A to ICR0D) or compare-match (CYLR6A to CYLR6D, CYLR7A to
CYLR7D), clearing by the DMAC has priority and the interrupt status flag is not set.
The timing in this case is shown in figure 11.69.
P
DMAC clear request
signal
Interrupt status flag
clear signal
Input capture/
compare-match signal
Interrupt status flag
ICF0A to ICF0D,
CMF6A to CMF6D,
CMF7A to CMF7D
Figure 11.69 Contention between Interrupt Status Flag Clearing by DMAC and Setting by Input
Capture/Compare-Match
Halting of a Down-Counter by the CPU: A down-counter (DCNT) can be halted by writing H'0000 to it. The CPU
cannot write 0 directly to the down-count start register (DSTR); instead, by setting DCNT to H'0000, the corresponding
DSTR bit is cleared to 0 and the count is stopped. However, the OSF bit in the timer status register (TSR) is set when
DCNT underflows.
Note that when H'0000 is written to DCNT, the corresponding DSTR bit is not cleared to 0 immediately; it is cleared to 0,
and the down-counter is stopped, when underflow occurs following the H'0000 write.
The timing in this case is shown in figure 11.70.
P
DCNT input clock
DCNT
Internal write signal
DSTR
TSR
N
H'0000
written
to DCNT
H'0000
H'0000
Port output
(one-shot pulse)
Figure 11.70 Halting of a Down-Counter by the CPU
Rev.3.00 Mar. 12, 2008 Page 319 of 948
REJ09B0177-0300