UPD78F1502AGK-GAK-AX Datasheet, PDF (999/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(27/39)
Page
LCD
ISC: Input switch Be sure to clear bits 5 to 7 to “0”.
p.674 _†
controller/d control register
river
Internal voltage When stopping the operation of the voltage boost circuit circuit, be sure to set SCOC p.679 _†
boosting method and LCDON to 0 before setting VLCON to 0.
Capacitor split When stopping the operation of the capacitor split circuit, be sure to set SCOC and p.680 _†
method
LCDON to 0 before setting VLCON to 0.
External
To stabilize the potential of the VLC0 to VLC3 pins, it is recommended to connect a pp.703 _†
resistance
capacitor of about 0.1 μF between each of the pins from VLC0 to VLC3 and the GND pin ,704
division method as needed.
Selection of LCD When the LCD display data memory is used when the number of time slices is eight, p.706 _†
display data
LCD display data (A-pattern, B-pattern, or blinking display) cannot be selected.
Multiplier/d MDAH, MDAL: Do not rewrite the MDAH and MDAL values during division operation processing p.711 _†
ivider
Multiplication/divi (while the multiplication/division control register (MDUC) is 81H). The operation will
sion data
be executed in this case, but the operation result will be an undefined value.
register A
The MDAH and MDAL values read during division operation processing (while p.711 _†
MDUC is 81H) will not be guaranteed.
MDBL, MDBH: Do not rewrite the MDBH and MDBL values during division operation processing p.711 _†
Multiplication/divi (while the multiplication/division control register (MDUC) is 81H). The operation
sion data
result will be an undefined value.
register B
Do not set MDBH and MDBL to 0000H in the division mode. If they are set, the p.711 _†
operation result will be an undefined value.
MDCL, MDCH: The MDCH and MDCL values read during division operation processing (while the p.712 _†
Multiplication/divi multiplication/division control register (MDUC) is 81H) will not be guaranteed.
sion data
register C
MDUC:
Do not rewrite DIVMODE during operation processing (while DIVST is 1). If it is p.713 _†
Multiplication/divi rewritten, the operation result will be an undefined value.
sion control
DIVST cannot be cleared (0) by using software during division operation processing p.713 _†
register
(while DIVST is 1).
DMA
DBCn: DMA
Be sure to clear bits 15 to 10 to “0”.
p.720 _†
controller byte count
If the general-purpose register is specified or the internal RAM space is exceeded as p.720 _†
register n
a result of continuous transfer, the general-purpose register or SFR space are written
or read, resulting in loss of data in these spaces. Be sure to set the number of times
of transfer that is within the internal RAM space.
DRCn: DMA
The DSTn flag is automatically cleared to 0 when a DMA transfer is completed. p.723 _†
operation control Writing the DENn flag is enabled only when DSTn = 0. When a DMA transfer is
register n
terminated without waiting for generation of the interrupt (INTDMAn) of DMAn,
therefore, set DSTn to 0 and then DENn to 0 (for details, refer to 18.5.7 Forced
termination by software).
When the FSEL bit of the OSMC register has been set to 1, do not enable (DENn = p.723 _†
1) DMA operation for at least three clocks after the setting.
Holding DMA When DMA transfer is held pending while using both DMA channels, be sure to held p.735 _†
transfer pending the DMA transfer pending for both channels (by setting DWAIT0 and DWAIT1 to 1).
by DWAITn
If the DMA transfer of one channel is executed while that of the other channel is held
pending, DMA transfer might not be held pending for the latter channel.
Forced
In example 3, the system is not required to wait two clock cycles after the DWAITn bit p.737 _†
termination of is set to 1. In addition, the system does not have to wait two clock cycles after
DMA transfer clearing the DSTn bit to 0, because more than two clock cycles elapse from when the
DSTn bit is cleared to 0 to when the DENn bit is cleared to 0.
R01UH0004EJ0501 Rev.5.01
983
Jun 20, 2011