UPD78F1502AGK-GAK-AX Datasheet, PDF (167/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 4 PORT FUNCTIONS
4.2.8 Port 7
<R>
P70/KR0
P71/KR1
P72/KR2
P73/KR3
P74/KR4
P75/SCK01
P76/KR6/SI01
P77/KR7/SO01
78K0R/LF3
(80 pins: μ PD78F15x0A,
78K0R/LG3
(100 pins: μ PD78F15x3A,
78F1501A, 78F15x2A)
78F1504A, 78F15x5A)
−
−
−
−
−
−
−
−
78K0R/LH3
(128 pins: μ PD78F15x6A,
78F1507A, 78F15x8A)
√
√
√
√
√
√
√
√
Port 7 is an I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port
mode register 7 (PM7). When the P70 to P77 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 7 (PU7).
Input to the P75 and P76 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using
port input mode register 7 (PIM7).
Output from the P75 and P77 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port
output mode register 7 (POM7).
This port can also be used for key return input, serial interface clock I/O, and data I/O.
Reset signal generation sets port 7 to input mode.
Figures 4-16 to 4-19 show block diagrams of port 7.
Caution To use P75/SCK01/KR5, P76/SI01/KR6, and P77/SO01/KR7, as a general-purpose port, note the serial
array unit 0 setting. For details, refer to Table 14-6 Relationship Between Register Settings and Pins
(Channel 1 of unit 0: CSI01, UART0 Reception).
R01UH0004EJ0501 Rev.5.01
151
Jun 20, 2011