UPD78F1502AGK-GAK-AX Datasheet, PDF (1007/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(35/39)
Page
Regulator
Option
byte
RMC: Regulator A wait is required to change the operation speed mode control register (OSMC) after p.828 _†
mode control changing the RMC register. Wait for 2 ms by software when setting to low-power
register
consumption mode and 10 μs when setting to normal power mode, as described in
the procedure shown below.
• When setting to low-power consumption mode
<1> Select a frequency of 1 MHz for fCLK.
<2> Set RMC to 5AH (set the regulator to low-power consumption mode).
<3> Wait for 2 ms.
<4> Set FLPC and FSEL of OSMC to 1 and 0, respectively.
• When setting to normal power mode
<1> Set RMC to 00H (set the regulator to normal power mode).
<2> Wait for 10 μs.
<3> Change FLPC and FSEL of OSMC.
<4> Change the fCLK frequency.
000C2H/010C2H Be sure to set FFH to 000C2H (000C2H/010C2H when the boot swap operation is p.829 _†
used).
000C0H/010C0H Set the same value as 000C0H to 010C0H when the boot swap operation is used p.829 _†
because 000C0H is replaced by 010C0H.
000C1H/010C1H Set the same value as 000C1H to 010C1H when the boot swap operation is used p.829 _†
because 000C1H is replaced by 010C1H.
000C2H/010C2H Set FFH to 010C2H when the boot swap operation is used because 000C2H is p.829 _†
replaced by 010C2H.
000C3H/010C3H Set the same value as 000C3H to 010C3H when the boot swap operation is used p.830 _†
because 000C3H is replaced by 010C3H.
000C0H/010C0H The watchdog timer continues its operation during self-programming of the flash p.831 _†
memory and EEPROM emulation. During processing, the interrupt acknowledge
time is delayed. Set the overflow time and window size taking this delay into
consideration.
000C1H/010C1H Be sure to set bits 7 to 3 to “1”.
p.832 _†
Even when the LVI default start function is used, if it is set to LVI operation p.832 _†
prohibition by the software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU
starts after reset release. There is a period when low-voltage detection cannot be
performed normally, however, when a reset occurs due to WDT and illegal
instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200 μs
max., LVION = 1 is set upon reset occurrence, and the CPU starts operating
without waiting for the LVI stabilization time.
000C3H/010C3H Bits 7 and 0 (OCDENSET and OCDERSD) can only be specified a value.
p.832 _†
Be sure to set 000010B to bits 6 to 1.
Setting of option To specify the option byte by using assembly language, use OPT_BYTE as the p.833 _†
byte
relocation attribute name of the CSEG pseudo instruction. To specify the option byte
to 010C0H to 010C3H in order to use the boot swap function, use the relocation
attribute AT to specify an absolute address.
R01UH0004EJ0501 Rev.5.01
991
Jun 20, 2011