UPD78F1502AGK-GAK-AX Datasheet, PDF (876/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 30 INSTRUCTION SET
30.2 Operation List
Table 30-5. Operation List (1/17)
Instruction Mnemonic
Group
Operands
Bytes
Clocks
Note 1 Note 2
Operation
Flag
Z AC CY
8-bit data MOV
transfer
r, #byte
saddr, #byte
2
1
− r ← byte
3
1
− (saddr) ← byte
sfr, #byte
3
1
− sfr ← byte
!addr16, #byte
4
A, r
Note 3
1
r, A
Note 3
1
1
− (addr16) ← byte
1
− A←r
1
− r←A
A, saddr
2
1
− A ← (saddr)
saddr, A
2
1
− (saddr) ← A
A, sfr
2
1
− A ← sfr
sfr, A
2
1
− sfr ← A
A, !addr16
3
1
4 A ← (addr16)
!addr16, A
3
1
− (addr16) ← A
PSW, #byte
3
3
− PSW ← byte
×××
A, PSW
2
1
− A ← PSW
PSW, A
2
3
− PSW ← A
×××
ES, #byte
2
1
− ES ← byte
ES, saddr
3
1
− ES ← (saddr)
A, ES
2
1
− A ← ES
ES, A
2
1
− ES ← A
CS, #byte
3
1
− CS ← byte
A, CS
2
1
− A ← CS
CS, A
2
1
− CS ← A
A, [DE]
1
1
4 A ← (DE)
[DE], A
1
1
− (DE) ← A
[DE + byte], #byte
3
1
− (DE + byte) ← byte
A, [DE + byte]
2
1
4 A ← (DE + byte)
[DE + byte], A
2
1
− (DE + byte) ← A
A, [HL]
1
1
4 A ← (HL)
[HL], A
1
1
− (HL) ← A
[HL + byte], #byte
3
1
− (HL + byte) ← byte
Notes 1.
2.
3.
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
When the program memory area is accessed.
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
R01UH0004EJ0501 Rev.5.01
860
Jun 20, 2011