UPD78F1502AGK-GAK-AX Datasheet, PDF (463/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
(1) Peripheral enable register 0 (PER0)
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that
is not used is stopped in order to reduce the power consumption and noise.
When serial array unit 0 is used, be sure to set bit 2 (SAU0EN) of this register to 1.
When serial array unit 1 is used, be sure to set bit 3 (SAU1EN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 14-4. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol
<7>
<6>
<5>
PER0
RTCEN
DACEN
ADCEN
<4>
IICAEN ^Note
<3>
SAU1EN
<2>
SAU0EN
<1>
TAU1EN
<0>
TAU0EN
SAUmEN
0
1
Control of serial array unit m input clock
Stops supply of input clock.
• SFR used by serial array unit m cannot be written.
• Serial array unit m is in the reset status.
Supplies input clock.
• SFR used by serial array unit m can be read/written.
Note 78K0R/LG3, 78K0R/LH3 only
Cautions 1. When setting serial array unit m, be sure to set SAUmEN to 1 first. If SAUmEN = 0, writing to a
control register of serial array unit m is ignored, and, even if the register is read, only the
default value is read (except for input switch control register (ISC), noise filter enable register
(NFEN0), port input mode registers (PIM1, PIM7), port output mode registers (POM1, POM7,
POM8), port mode registers (PM1, PM5, PM7, PM8), and port registers (P1, P5, P7, P8)).
2. After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
Remark m: Unit number (m = 0, 1)
(2) Serial clock select register m (SPSm)
SPSm is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly
supplied to each channel. CKm1 is selected by bits 7 to 4 of SPSm, and CKm0 is selected by bits 3 to 0.
Rewriting SPSm is prohibited when the register is in operation (when SEmn = 1).
SPSm can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of SPSm can be set with an 8-bit memory manipulation instruction with SPSmL.
Reset signal generation clears this register to 0000H.
R01UH0004EJ0501 Rev.5.01
447
Jun 20, 2011