UPD78F1502AGK-GAK-AX Datasheet, PDF (260/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 5 CLOCK GENERATOR
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (4/6)
(9) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(C) → (D)
CSC Register
XTSTOP
0
Waiting for Oscillation
Stabilization
Necessary
CKC Register
CSS
1
Unnecessary if the CPU is operating with the
subsystem clock
(10) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(D) → (B)
CSC Register
HIOSTOP
0
CKC Register
MCM0
0
CSS
0
Unnecessary if the CPU
is operating with the
internal high-speed
oscillation clock
Unnecessary if this
register is already set
Remark (A) to (K) in Table 5-4 correspond to (A) to (K) in Figure 5-15.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011