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UPD78F1502AGK-GAK-AX Datasheet, PDF (885/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers | |||
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78K0R/Lx3
CHAPTER 30 INSTRUCTION SET
Table 30-5. Operation List (10/17)
Instruction Mnemonic
Group
Operands
Bytes
Clocks
Note 1 Note 2
Operation
Flag
Z AC CY
8-bit
CMP
operation
A, #byte
2
saddr, #byte
3
A, r
Note 3
2
1
â A â byte
1
â (saddr) â byte
1
â Aâr
ÃÃÃ
ÃÃÃ
ÃÃÃ
r, A
2
1
â râA
ÃÃÃ
A, saddr
2
1
â A â (saddr)
ÃÃÃ
A, !addr16
3
1
4 A â (addr16)
ÃÃÃ
A, [HL]
1
1
4 A â (HL)
ÃÃÃ
A, [HL + byte]
2
1
4 A â (HL + byte)
ÃÃÃ
A, [HL + B]
2
1
4 A â (HL + B)
ÃÃÃ
A, [HL + C]
2
1
4 A â (HL + C)
ÃÃÃ
!addr16, #byte
4
1
4 (addr16) â byte
ÃÃÃ
A, ES:!addr16
4
2
5 A â (ES:addr16)
ÃÃÃ
A, ES:[HL]
2
2
5 A â (ES:HL)
ÃÃÃ
A, ES:[HL + byte]
3
2
5 A â ((ES:HL) + byte)
ÃÃÃ
A, ES:[HL + B]
3
2
5 A â ((ES:HL) + B)
ÃÃÃ
A, ES:[HL + C]
3
2
5 A â ((ES:HL) + C)
ÃÃÃ
ES:!addr16, #byte
5
2
5 (ES:addr16) â byte
ÃÃÃ
CMP0 A
1
1
â A â 00H
ÃÃÃ
X
1
1
â X â 00H
ÃÃÃ
B
1
1
â B â 00H
ÃÃÃ
C
1
1
â C â 00H
ÃÃÃ
saddr
2
1
â (saddr) â 00H
ÃÃÃ
!addr16
3
1
4 (addr16) â 00H
ÃÃÃ
ES:!addr16
4
2
5 (ES:addr16) â 00H
ÃÃÃ
CMPS X, [HL + byte]
3
1
4 X â (HL + byte)
ÃÃÃ
X, ES:[HL + byte]
4
2
5 X â ((ES:HL) + byte)
ÃÃÃ
Notes 1.
2.
3.
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
When the program memory area is accessed.
Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
R01UH0004EJ0501 Rev.5.01
869
Jun 20, 2011
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