UPD78F1502AGK-GAK-AX Datasheet, PDF (642/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
(1) Master device operation
(a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception)
(i) When WTIM = 0
ST AD6 to AD0 R/W ACK
D7 to D0
1
ACK
2
D7 to D0
SPT = 1
↓
ACK SP
3 45
1: IICS = 1000×110B
2: IICS = 1000×000B
3: IICS = 1000×000B (Sets WTIM to 1)^Note
4: IICS = 1000××00B (Sets SPT to 1)^Note
5: IICS = 00000001B
Note To generate a stop condition, set WTIM to 1 and change the timing for generating the INTIICA interrupt
request signal.
Remark : Always generated
: Generated only when SPIE = 1
×: Don’t care
(ii) When WTIM = 1
ST AD6 to AD0 R/W ACK
D7 to D0
1
ACK
D7 to D0
2
SPT = 1
↓
ACK SP
34
1: IICS = 1000×110B
2: IICS = 1000×100B
3: IICS = 1000××00B (Sets SPT to 1)
4: IICS = 00000001B
Remark : Always generated
: Generated only when SPIE = 1
×: Don’t care
R01UH0004EJ0501 Rev.5.01
626
Jun 20, 2011