UPD78F1502AGK-GAK-AX Datasheet, PDF (670/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
The following describes the operations in Figure 15-32 (4) Data ~ restart condition ~ address. After the operations
in steps <7> and <8>, the operations in steps <1> to <3> are performed. These steps return the processing to step
<3>, the data transmission step.
<7> When data transfer is complete, the slave device sends an ACK by hardware to the master device. The
ACK is detected by the master device (ACKD = 1) at the rising edge of the 9th clock.
<8> The master device and slave device set a wait status (SCL0 = 0) at the falling edge of the 9th clock, and
both the master device and slave device issue an interrupt (INTIICA: end of transfer).
<i> The slave device reads the received data and releases the wait status (WREL = 1).
<ii> The start condition trigger is set again by the master device (STT = 1) and a start condition (SDA0 = 0 and
SCL0 = 1) is generated once the bus clock line goes high (SCL0 = 1) and the bus data line goes low (SDA0
= 0) after the restart condition setup time has elapsed. When the start condition is subsequently detected,
the master device is ready to communicate once the bus clock line goes low (SCL0 = 0) after the hold time
has elapsed.
<iii> The master device writes the address + R/W (transmission) to the IICA shift register (IICA) and transmits
the slave address.
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Jun 20, 2011