UPD78F1502AGK-GAK-AX Datasheet, PDF (832/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 24 LOW-VOLTAGE DETECTOR
Figure 24-7. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Bit: LVISEL = 1)
Input voltage from
external input pin (EXLVI)
VEXLVI
Set LVI to be
used for reset
LVIMK flag H^{Note 1}
(set by software)
<1>
LVISEL flag
(set by software)
<2>
Not cleared
LVION flag
(set by software)
LVIF flag
LVIMD flag
(set by software)
Not cleared
<3>
<4> Wait time
Note 2 <5>
<6>
Not cleared
LVIRF flag^{Note 3}
Not cleared
Not cleared
Not cleared
Time
Not cleared
Not cleared
Not cleared
LVI reset signal
Internal reset signal
Cleared by
software
Cleared by
software
Notes 1.
2.
3.
The LVIMK flag is set to “1” by reset signal generation.
The LVIIF flag of the interrupt request flag registers and the LVIF flag may be set (1).
LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 22 RESET
FUNCTION.
Remark <1> to <6> in Figure 24-7 above correspond to <1> to <6> in the description of “When starting operation” in
24.4.1 (2) When detecting level of input voltage from external input pin (EXLVI).
R01UH0004EJ0501 Rev.5.01
816
Jun 20, 2011