UPD78F1502AGK-GAK-AX Datasheet, PDF (974/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(2/39)
Page
Pin
P20/ANI0/AMP0- P20/ANI0/AMP0- to P27/ANI7/ANP2O are set in the digital input (general-purpose p.46 _†
functions to
port) mode after release of reset.
P27/ANI7/ANP2O When using at least one port of ports P20/ANI0/AMP0- to P27/ANI7/ANP2O as a p.46 _†
digital port, set AVDD0 to the same potential as EVDD or VDD.
P30/TO00/TI03/ To use P30/TO00/TI03/RTC1HZ/INTP1 as a general-purpose port, set bit 5 p.48 _†
RTC1HZ/INTP1 (RCLOE1) of real-time counter control register 0 (RTCC0), bit 0 (TO00) of timer
output register 0 (TO0) and bit 0 (TOE00) of timer output enable register 0 (TOE0) to
“0”, which is the same as their default status setting.
P31/TO03/TI00/ To use P31/TO03/TI00/RTCDIV/RTCCL/PCLBUZ1/INTP2 as a general-purpose port, p.48 _†
RTCDIV/RTCCL/ set bit 4 (RCLOE0) of real-time counter control register 0 (RTCC0), bit 6 (RCLOE2)
PCLBUZ1/INTP2 of real-time counter control register 2 (RTCC2), bit 3 (TO03) of timer output register 0
(TO0), bit 3 (TOE03) of timer output enable register 0 (TOE0) and bit 7 of clock
output select register 1 (CKS1) to “0”, which is the same as their default status
setting.
P32/TO01/TI01/ To use P32/TO01/TI01/INTP5/PCLBUZ0 as a general-purpose port, set bit 1 (TO01) p.48 _†
INTP5/PCLBUZ0 of timer output register 0 (TO0), bit 1 (TOE01) of timer output enable register 0
(TOE0) and bit 7 of clock output select register 0 (CKS0) to “0”, which is the same as
their default status setting.
P33/TO07/TI07/ ^{To use P33/TO07/TI07/INTP3 and P34/TO06/TI06/INTP8 as a general-purpose port, p.48} †
INTP3,
set bit 7, 6 (TO07, TO06) of timer output register 0 (TO0), and bit 7, 6 (TOE07,
P34/TO06/TI06/ ^{TOE06) of timer output enable register 0 (TOE0) to “0”, which is the same as their}
INTP8
P40/TOOL0
default status setting.
The function of the P40/TOOL0 pin varies as described in (a) to (c) below.
p.49 _†
In the case of (b) or (c), make the specified connection.
(a) In normal operation mode and when on-chip debugging is disabled (OCDENSET
= 0) by an option byte (000C3H)
=> Use this pin as a port pin (P40).
(b) In normal operation mode and when on-chip debugging is enabled (OCDENSET
= 1) by an option byte (000C3H)
=> Connect this pin to VDD via an external resistor, and always input a high level
to the pin before reset release.
(c) When on-chip debug function is used, or in write mode of flash memory
programmer
=> Use this pin as TOOL0. Directly connect this pin to the on-chip debug
emulator or a flash memory programmer, or pull it up by connecting it to VDD
via an external resistor.
P60/SCL0,
When using P60/SCL0 and P61/SDA0 as a general-purpose port, stop the operation p.50 _†
P61/SDA0
of serial interface IICA.
P75/SCK01/KR5, ^{To use P75/SCK01/KR5, P76/SI01/KR6, and P77/SO01/KR7, as a general-purpose p.51} †
P76/SI01/KR6, ^{port, note the serial array unit 0 setting. For details, refer to Table 14-6 Relationship}
P77/SO01/KR7 ^{Between Register Settings and Pins (Channel 1 of unit 0: CSI01, UART0 Reception).}
P80/SCK00/
To use P80/SCK00/INTP11, P81/RxD0/SI00/INTP9, and P82/SO00/TxD0, as a p.53 _†
INTP11,
general-purpose port, note the serial array unit 0 setting. For details, refer to Table
P81/RxD0/SI00/ 14-5 Relationship Between Register Settings and Pins (Channel 0 of unit 0: CSI00,
INTP9,
UART0 Reception).
P82/SO00/TxD0
R01UH0004EJ0501 Rev.5.01
958
Jun 20, 2011