UPD78F1502AGK-GAK-AX Datasheet, PDF (288/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
Figure 6-11. Start Timing (In Interval Timer Mode)
fCLK
TSmn (write)
TEmn ^<1>
Count clock
TSmn (write) hold signal
<2>
Start trigger detection signal
TCRmn
<3>
Initial value
<4>
TDRmn value
INTTMmn
When MDmn0 = 1 is set
Caution In the first cycle operation of count clock after writing TSmn, an error at a maximum of one clock
is generated since count start delays until count clock has been generated. When the information
on count start timing is necessary, an interrupt can be generated at count start by setting MDmn0
= 1.
Remark mn: Unit number + Channel number
mn = 00 to 07, 10 to 13
(b) Start timing in event counter mode
<1> While TEpq is set to 0, TCRpq holds the initial value.
<2> Writing 1 to TSpq sets 1 to TEpq.
<3> As soon as 1 has been written to TSpq and 1 has been set to TEpq, the "TDRpq value" is loaded to
TCRpq to start counting.
<4> After that, the TCRpq value is counted down according to the count clock.
Figure 6-12. Start Timing (In Event Counter Mode)
fCLK
TSpq (write)
TEpq ^<1>
<2>
Count clock
TSpq (write) hold signal
Start trigger detection signal
<1>
<3>
TCRpq Initial value
TDRpq value
TDRpq value-1
Remark
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
R01UH0004EJ0501 Rev.5.01
272
Jun 20, 2011