UPD78F1502AGK-GAK-AX Datasheet, PDF (208/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 4 PORT FUNCTIONS
(5) Port output mode registers (POMx)
These registers set the output mode of P10 to P15, P75, P77, P80, or P82 in 1-bit units.
N-ch open drain output (VDD tolerance) mode can be selected during serial communication with an external device of
the different potential, and for the SDA10, SDA20 pin during simplified I²C communication with an external device of
the same potential.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
• 78K0R/LF3
Figure 4-48. Format of Port Output Mode Register
Symbol
7
POM1
0
6
5
4
3
2
1
0
Address After reset R/W
0
POM15 POM14 POM13 POM12 POM11 POM10 F0051H
00H
R/W
• 78K0R/LG3
Symbol
7
POM1
0
6
5
4
3
2
1
0
Address After reset R/W
0
POM15 POM14 POM13 POM12 POM11 POM10 F0051H
00H
R/W
POM8
0
0
0
0
0
POM82
0
POM80 F0058H
00H
R/W
• 78K0R/LH3
Symbol
7
POM1
0
6
5
4
3
2
1
0
Address After reset R/W
0
POM15 POM14 POM13 POM12 POM11 POM10 F0051H
00H
R/W
POM7 POM77
0
POM75
0
0
0
0
0
F0057H
00H
R/W
POM8
0
0
0
0
0
POM82
0
POM80 F0058H
00H
R/W
POMmn
Pmn pin output mode selection
(m = 1, 7, and 8; n = 0 to 5 and 7)
0
Normal output mode
1
N-ch open-drain output (VDD tolerance) mode
R01UH0004EJ0501 Rev.5.01
192
Jun 20, 2011