UPD78F1502AGK-GAK-AX Datasheet, PDF (272/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
Figure 6-1. Block Diagram of Timer Array Unit 0
Peripheral enable
register 0 TAU0EN
(PER0)
Timer clock select register 0 (TPS0)
PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000
4
4
fCLK
Prescaler
fCLK/2⁰ to fCLK/2¹⁵
fCLK/2⁰ to fCLK/2¹⁵
Selector
Selector
fSUBC/2
TIS00, RTCIS00, SDIV
3
Timer channel
TE07 TE06 TE05 TE04 TE03 TE02 TE01 TE00 enable status
register 0 (TE0)
Timer channel
TS07 TS06 TS05 TS04 TS03 TS02 TS01 TS00 start register 0
(TS0)
Timer channel
TT07 TT06 TT05 TT04 TT03 TT02 TT01 TT00 stop register 0
(TT0)
Timer input
TIS07 TIS06 TIS05 TIS04 TIS03 TIS02 TIS01 TIS00 select register 0
(TIS0)
0
0 ^{RTCIS RTCIS}
04 00
Bits 0 to 3 are used
by timer array unit 1
Timer input
select register 1
(TIS1)
TNFEN
07
TNFEN TNFEN
06 05
TNFEN
04
TNFEN
03
TNFEN TNFEN TNFEN
02 01 00
Noise filter
enable register 1
(NFEN1)
Timer output
TOE07 TOE06 TOE05 TOE04 TOE03 TOE02 TOE01 TOE00 enable register 0
(TOE0)
Timer output
TO07 TO06 TO05 TO04 TO03 TO02 TO01 TO00 register 0
(TO0)
Timer output
TOM07 TOM06 TOM05 TOM04 TOM03 TOM02 TOM01 TOM00 mode register 0
(TOM0)
Timer output
TOL07 TOL06 TOL05 TOL04 TOL03 TOL02 TOL01 TOL00 level register 0
(TOL0)
RTC interval
interrupt
(INTRTCI)
: fXT/2⁶ to fXT/2¹²
Noise elimination
enabled/disabled
TI00
Channel 0
CK00
CK01
fSUBC/2
MCK
Edge
detection
Slave/master
controller
Trigger signal to slave channel
Clock signal to slave channel
Interrupt signal to slave channel
TCLK Timer controller
Mode
selection
TO00
INTTM00
Output
controller
Interrupt
controller
Output latch
(P32)
PM32
TO01
(Timer
output pin)
INTTM01
(Timer
interrupt)
TI01
(Timer
input pin)
TIS01
TNFEN01
Channel 1
Slave/master
controller
Timer counter register 01 (TCR01)
Timer data register 01 (TDR01)
Timer status
register 01 (TSR01)
OVF
Overflow 01
CKS01
CCS01
MAS
TER01
STS012 STS011
STS010
CIS011 CIS010
MD013
MD012
MD011
MD010
Timer mode register 01 (TMR01)
TI02
Channel 2
TI03
Channel 3
fSUBC/2
TIS04, RTCIS04, SDIV
3
TO02
INTTM02
A/D converter
(ADTMD = 1, ADTRS = 0 setting)
TO03
INTTM03
A/D converter
(ADTMD = 1, ADTRS = 1 setting)
RTC interval
interrupt
(INTRTCI)
: fXT/2⁶ to fXT/2¹²
Noise elimination
enabled/disabled
TI04
Channel 4
TO04
INTTM04
Channel 0 of the D/A converter
(DAMD0 = 1 setting)
TI05
Channel 5
TI06
TI07
RxD3
(Serial input pin)
Channel 6
ISC1
Channel 7 (LIN-bus supported)
TO05
INTTM05
Channel 1 of the D/A converter
(DAMD1 = 1 setting)
TO06
INTTM06
TO07
INTTM07
Remark Channels 5 and 6 of the 78K0R/LF3 are not provided with timer I/O pins (TI05/TO05, TI06/TO06).
R01UH0004EJ0501 Rev.5.01
256
Jun 20, 2011