UPD78F1502AGK-GAK-AX Datasheet, PDF (804/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 22 RESET FUNCTION
CHAPTER 22 RESET FUNCTION
The following five operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage of the low-voltage detector (LVI) or input voltage (EXLVI) from
external input pin, and detection voltage
(5) Internal reset by execution of illegal instruction^Note
External and internal resets start program execution from the address at 0000H and 0001H when the reset signal is
generated.
A reset is effected when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI circuit
voltage detection or execution of illegal instruction^Note, and each item of hardware is set to the status shown in Tables 22-1
and 22-2. Each pin is high impedance during reset signal generation or during the oscillation stabilization time just after a
reset release, except for P130, which is low-level output.
When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high level is
input to the RESET pin and program execution is started with the internal high-speed oscillation clock after reset
processing. A reset by the watchdog timer is automatically released, and program execution starts using the internal high-
speed oscillation clock (see Figures 22-2 to 22-4) after reset processing. Reset by POC and LVI circuit power supply
detection is automatically released when VDD ≥ VPOR or VDD ≥ VLVI after the reset, and program execution starts using the
internal high-speed oscillation clock (see CHAPTER 23 POWER-ON-CLEAR CIRCUIT and CHAPTER 24 LOW-
VOLTAGE DETECTOR) after reset processing.
Note
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
Cautions 1. For an external reset, input a low level for 10 μs or more to the RESET pin
(To perform an external reset upon power application, a low level of at least 10 μs must be
continued during the period in which the supply voltage is within the operating range (VDD ≥ 1.8
V)).
2. During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and internal
low-speed oscillation clock stop oscillating. External main system clock input becomes invalid.
3. When the STOP mode is released by a reset, the RAM contents in the STOP mode are held during
reset input.
4. When reset is effected, port pin P140 is set to low-level output and other port pins become high-
impedance, because each SFR and 2nd SFR are initialized.
Remark VPOR: POC power supply rise detection voltage
VLVI: LVI detection voltage
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011