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UPD78F1502AGK-GAK-AX Datasheet, PDF (634/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers
78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
(1) Master operation in single-master system
Figure 15-28. Master Operation in Single-Master System
START
Initializing I2C busNote
Setting port
Setting of the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see 15.3 (8) Port mode register 6 (PM6)).
IICWL, IICWH ← XXH
Sets a transfer clock.
SVA ← XXH
Sets a local address.
IICF ← 0XH
Setting STCEN, IICRSV = 0
IICCTL0 ← 0XX111XXB
ACKE = WTIM = SPIE = 1
IICCTL0 ← 1XX111XXB
IICE = 1
Setting port
Sets a start condition.
Set the port from input mode to output mode and enable the output of the I2C bus
(see 15.3 (8) Port mode register 6 (PM6)).
STCEN = 1?
No
SPT = 1
Yes
Prepares for starting communication
(generates a stop condition).
INTIICA
interrupt occurs?
Yes
No
Waits for detection of the stop condition.
STT = 1
Writing IICA
Prepares for starting communication
(generates a start condition).
Starts communication
(specifies an address and transfer
direction).
INTIICA
interrupt occurs?
Yes
No
Waits for detection of acknowledge.
No
ACKD = 1?
Yes
TRC = 1?
No
Yes
Writing IICA
Starts transmission.
INTIICA
interrupt occurs?
Yes
No
Waits for data transmission.
ACKD = 1?
No
Yes
No
End of transfer?
Yes
Restart?
Yes
No
SPT = 1
END
ACKE = 1
WTIM = 0
WREL = 1
Starts reception.
INTIICA
interrupt occurs?
Yes
Reading IICA
No
Waits for data
reception.
End of transfer?
No
Yes
ACKE = 0
WTIM = WREL = 1
INTIICA
interrupt occurs?
Yes
No
Waits for detection
of acknowledge.
Note Release (SCL0 and SDA0 pins = high level) the I2C bus in conformance with the specifications of the product
that is communicating. If EEPROM is outputting a low level to the SDA0 pin, for example, set the SCL0 pin in
the output port mode, and output a clock pulse from the output port until the SDA0 pin is constantly at high level.
Remark Conform to the specifications of the product that is communicating, with respect to the transmission and
reception formats.
R01UH0004EJ0501 Rev.5.01
618
Jun 20, 2011