UPD78F1502AGK-GAK-AX Datasheet, PDF (747/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 18 DMA CONTROLLER
18.5.4 Consecutive capturing of A/D conversion results
A flowchart of an example of setting for consecutively capturing A/D conversion results is shown below.
• Consecutive capturing of A/D conversion results.
• DMA channel 1 is used for DMA transfer.
• DMA start source: INTAD
• Interrupt of A/D is specified by IFC13 to IFC10 (bits 3 to 0 of the DMC1 register) = 1100B.
• Transfers FFF1EH and FFF1FH (2 bytes) of the 12-bit A/D conversion result register to 512 bytes of FFCE0H to
FFEDFH of RAM.
R01UH0004EJ0501 Rev.5.01
731
Jun 20, 2011