UPD78F1502AGK-GAK-AX Datasheet, PDF (600/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
15.3 Registers Controlling Serial Interface IICA
Serial interface IICA is controlled by the following eight registers.
• Peripheral enable register 0 (PER0)
• IICA control register 0 (IICCTL0)
• IICA flag register (IICF)
• IICA status register (IICS)
• IICA control register 1 (IICCTL1)
• IICA low-level width setting register (IICWL)
• IICA high-level width setting register (IICWH)
• Port mode register 6 (PM6)
• Port register 6 (P6)
(1) Peripheral enable register 0 (PER0)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a
hardware macro that is not used is stopped in order to reduce the power consumption and noise.
When serial interface IICA is used, be sure to set bit 4 (IICAEN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 15-5. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol
<7>
<6>
<5>
PER0
RTCEN
DACEN
ADCEN
<4>
IICAEN^Note
<3>
SAU1EN
<2>
SAU0EN
<1>
TAU1EN
<0>
TAU0EN
IICAEN
0
1
Control of serial interface IICA input clock
Stops supply of input clock.
• SFR used by serial interface IICA cannot be written.
• Serial interface IICA is in the reset status.
Supplies input clock.
• SFR used by serial interface IICA can be read/written.
Note 78K0R/LG3, 78K0R/LH3 only
Caution
When setting serial interface IICA, be sure to set IICAEN to 1 first. If IICAEN = 0, writing to a
control register of serial interface IICA is ignored, and, even if the register is read, only the
default value is read.
(2) IICA control register 0 (IICCTL0)
This register is used to enable/stop I²C operations, set wait timing, and set other I²C operations.
IICCTL0 can be set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIE, WTIM, and ACKE
bits while IICE bit = 0 or during the wait period. These bits can be set at the same time when the IICE bit is set
from “0” to “1”.
Reset signal generation clears this register to 00H.
R01UH0004EJ0501 Rev.5.01
584
Jun 20, 2011