UPD78F1502AGK-GAK-AX Datasheet, PDF (936/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
(3) Serial interface: IICA
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
(a) IICA
Parameter
Symbol
Conditions
SCL0 clock frequency
fSCL
Setup time of restart condition^{Note 1}
Hold time
Hold time when SCL0 = “L”
Hold time when SCL0 = “H”
Data setup time (reception)
Data hold time (transmission)^{Note 2}
Setup time of stop condition
Bus-free time
tSU:STA
tHD:STA
tLOW
tHIGH
tSU:DAT
tHD:DAT
tSU:STO
tBUF
Fast mode: fCLK ≥3.5 MHz,
Standard mode: fCLK ≥1 MHz
Standard Mode
MIN.
MAX.
0
100
High-Speed Mode Unit
MIN. MAX.
0
400 kHz
4.7
0.6
μs
4.0
0.6
μs
4.7
1.3
μs
4.0
0.6
μs
250
100
ns
0
3.45
0
0.9 μs
4.0
0.6
μs
4.7
1.3
μs
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Remark fCLK: CPU/peripheral hardware clock frequency
IICA serial transfer timing
tLOW
SCL0
tHD:DAT
tHD:STA
tHIGH
tSU:DAT
tSU:STA
tHD:STA
tSU:STO
SDA0
tBUF
Stop
Start
condition condition
Restart
condition
Stop
condition
R01UH0004EJ0501 Rev.5.01
920
Jun 20, 2011