UPD78F1502AGK-GAK-AX Datasheet, PDF (352/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
Figure 6-66. Operation Procedure of One-Shot Pulse Output Function (2/2)
Software Operation
Hardware Status
Operation
start
Sets TOEmp (slave) to 1 (only when operation is
resumed).
The TSmn (master) and TSmp (slave) bits of the TSm
register are set to 1 at the same time.
The TSmn and TSmp bits automatically return to 0
because they are trigger bits.
TEmn and TEmp are set to 1 and the master channel
enters the TImn input edge detection wait status.
Counter stops operating.
Detects the start trigger of master channel.
Master channel starts counting.
(The valid edge of the TImn pin input is detected or the
TSmn bit is set to 1.)
During
operation
Set values of only the CISmn1 and CISmn0 bits of the
TMRmn register can be changed.
Set values of the TMRmp, TDRmn, and TDRmp registers
and TOMmn, TOMmp, TOLmn, and TOLmp bits cannot
be changed.
The TCRmn and TCRmp registers can always be read.
The TSRmn and TSRmp registers are not used.
Set values of the TOm and TOEm registers can be
changed.
Master channel loads the value of TDRmn to TCRmn
when the start trigger is detected, and the counter starts
counting down. When the count value reaches TCRmn =
0000H, the INTTMmn output is generated, and the counter
stops until the next valid edge is input to the TImn pin.
The slave channel, triggered by INTTMmn of the master
channel, loads the value of TDRmp to TCRmp, and the
counter starts counting down. The output level of TOmp
becomes active one count clock after generation of
INTTMmn from the master channel. It becomes inactive when
TCRmp = 0000H, and the counting operation is stopped.
After that, the above operation is repeated.
Operation
stop
The TTmn (master) and TTmp (slave) bits are set to 1 at
the same time.
The TTmn and TTmp bits automatically return to 0
because they are trigger bits.
TEmn, TEmp = 0, and count operation stops.
TCRmn and TCRmp hold count value and stops.
The TOmp output is not initialized but holds current
status.
TOEmp of slave channel is cleared to 0 and value is set
to the TOm register.
The TOmp pin outputs the TOmn set level.
TAU stop
To hold the TOmp pin output levels
Clears TOmp bit to 0 after the value to
be held is set to the port register.
When holding the TOmp pin output levels is not
necessary
Switches the port mode register to input mode.
The TAU0EN or TAU1EN bits of the PER0 register is
cleared to 0.
The TOmp pin output levels is held by port function.
The TOmp pin output levels go are into Hi-Z output state.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp bit is cleared to 0 and the TOmp pin is set to
port mode.)
Remarks 1.
2.
3.
78K0R/LF3:
• m = 0, n = 0, 2, 6, p = n+1, TO00 to TO04, and TO07 pins
• Channel 6 of timer array unit 0 can output a one-shot pulse only when software trigger start is selected
and it is used as the master channel (because the TI06 pin is not provided).
78K0R/LG3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
78K0R/LH3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07 pins
• m = 1, n = 0, 2, p = n+1, TO10 to TO13 pins
R01UH0004EJ0501 Rev.5.01
336
Jun 20, 2011