UPD78F1502AGK-GAK-AX Datasheet, PDF (928/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (11/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
(f) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output)
(1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCKp cycle time
tKCY1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 400 ^{Note 1}
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb < 2.7 V, 800 ^{Note 1}
ns
Cb = 30 pF, Rb = 2.7 kΩ
SCKp high-level width
tKH1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 − 75
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb < 2.7 V, tKCY1/2 −
ns
Cb = 30 pF, Rb = 2.7 kΩ
170
SCKp low-level width
tKL1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 − 20
ns
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb < 2.7 V, tKCY1/2 − 35
ns
Cb = 30 pF, Rb = 2.7 kΩ
SIp setup time
tSIK1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
150
ns
(to SCKp↑) ^{Note 2}
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb < 2.7 V,
275
ns
Cb = 30 pF, Rb = 2.7 kΩ
SIp hold time
tKSI1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
30
ns
(from SCKp↑) ^{Note 2}
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb < 2.7 V,
30
ns
Cb = 30 pF, Rb = 2.7 kΩ
Delay time from SCKp↓ to
SOp output ^{Note 2}
tKSO1
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
120
ns
2.7 V ≤ VDD ≤ 4.0 V, 2.3 V ≤ Vb < 2.7 V,
215
ns
Cb = 30 pF, Rb = 2.7 kΩ
Notes 1. The value must also be 4/fCLK or more.
2. When DAP0n = 0 and CKP0n = 0, or DAP0n = 1 and CKP0n = 1.
Caution Select the TTL input buffer for SIp and the N-ch open drain output (VDD tolerance) mode for SOp and
SCKp by using the PIMg and POMx registers.
Remarks 1. p: CSI number (p = 00, 01, 10, 20), g: PIM number (g = 1, 7), x: POM number (x = 1, 7, 8)
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
3. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance,
Cb[F]: Communication line (SIp, SOp, SCKp) load capacitance, Vb[V]: Communication line voltage
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in CSI mode.
4.0 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ VDD = EVDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V: VIH = 2.0 V, VIL = 0.5 V
R01UH0004EJ0501 Rev.5.01
912
Jun 20, 2011