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| UPD78F1502AGK-GAK-AX Datasheet, PDF (890/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers | |||
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78K0R/Lx3
CHAPTER 30 INSTRUCTION SET
Table 30-5. Operation List (15/17)
Instruction Mnemonic
Group
Operands
Bytes
Clocks
Note 1 Note 2
Operation
Flag
Z AC CY
Call/
CALL
rp
return
2
3
â (SP â 2) â (PC + 2)S, (SP â 3) â (PC + 2)H,
(SP â 4) â (PC + 2)L, PC â CS, rp,
SP â SP â 4
$!addr20
3
3
â (SP â 2) â (PC + 3)S, (SP â 3) â (PC + 3)H,
(SP â 4) â (PC + 3)L, PC â PC + 3 +
jdisp16,
SP â SP â 4
!addr16
3
3
â (SP â 2) â (PC + 3)S, (SP â 3) â (PC + 3)H,
(SP â 4) â (PC + 3)L, PC â 0000, addr16,
SP â SP â 4
!!addr20
4
3
â (SP â 2) â (PC + 4)S, (SP â 3) â (PC + 4)H,
(SP â 4) â (PC + 4)L, PC â addr20,
SP â SP â 4
CALLT [addr5]
2
5
â (SP â 2) â (PC + 2)S, (SP â 3) â (PC + 2)H,
(SP â 4) â (PC + 2)L , PCS â 0000,
PCH â (0000, addr5 + 1),
PCL â (0000, addr5),
SP â SP â 4
BRK
â
2
5
â (SP â 1) â PSW, (SP â 2) â (PC + 2)S,
(SP â 3) â (PC + 2)H, (SP â 4) â (PC + 2)L,
PCS â 0000,
PCH â (0007FH), PCL â (0007EH),
SP â SP â 4, IE â 0
RET
â
1
6
â PCL â (SP), PCH â (SP + 1),
PCS â (SP + 2), SP â SP + 4
RETI
â
2
6
â PCL â (SP), PCH â (SP + 1),
RRR
PCS â (SP + 2), PSW â (SP + 3),
SP â SP + 4
RETB
â
2
6
â PCL â (SP), PCH â (SP + 1),
RRR
PCS â (SP + 2), PSW â (SP + 3),
SP â SP + 4
Notes 1. When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
2. When the program memory area is accessed.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the system clock control
register (CKC).
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
R01UH0004EJ0501 Rev.5.01
874
Jun 20, 2011
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