UPD78F1502AGK-GAK-AX Datasheet, PDF (617/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
15.5.5 Stop condition
When the SCL0 pin is at high level, changing the SDA0 pin from low level to high level generates a stop condition.
A stop condition is a signal that the master device generates to the slave device when serial transfer has been
completed. When the device is used as a slave, stop conditions can be detected.
Figure 15-19. Stop Condition
H
SCL0
SDA0
A stop condition is generated when bit 0 (SPT) of IICA control register 0 (IICCTL0) is set to 1. When the stop condition
is detected, bit 0 (SPD) of the IICA status register (IICS) is set to 1 and INTIICA is generated when bit 4 (SPIE) of IICCTL0
is set to 1.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011