UPD78F1502AGK-GAK-AX Datasheet, PDF (963/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
APPENDIX B REGISTER INDEX
APPENDIX B REGISTER INDEX
B.1 Register Index (In Alphabetical Order with Respect to Register Names)
A
A/D converter mode register (ADM) ........................................................................................................................... 391
A/D converter mode register 1 (ADM1) ...................................................................................................................... 394
A/D port configuration register (ADPC) ...................................................................................................... 193, 399, 429
Alarm hour register (ALARMWH) ............................................................................................................................... 359
Alarm minute register (ALARMWM) ........................................................................................................................... 359
Alarm week register (ALARMWW) ............................................................................................................................. 360
Analog input channel specification register (ADS)...................................................................................................... 398
Analog reference voltage control register (ADVRC) ........................................................................................... 395, 435
B
Background event control register (BECTL)............................................................................................................... 839
BCD correction result register (BCDADJ)................................................................................................................... 854
C
Clock operation mode control register (CMC) ............................................................................................................ 209
Clock operation status control register (CSC) ............................................................................................................ 211
Clock output selection register 0 (CKS0).................................................................................................................... 382
Clock output selection register 1 (CKS1).................................................................................................................... 382
D
D/A conversion value setting register 0 (DACS0)....................................................................................................... 422
D/A conversion value setting register 1 (DACS1)....................................................................................................... 422
D/A conversion value setting register W0 (DACSW0) ................................................................................................ 422
D/A conversion value setting register W1 (DACSW1) ................................................................................................ 422
D/A converter mode register (DAM) ........................................................................................................................... 421
Day count register (DAY) ........................................................................................................................................... 355
DMA byte count register n (DBCn) ............................................................................................................................. 720
DMA mode control register n (DMCn) ........................................................................................................................ 721
DMA operation control register n (DRCn)................................................................................................................... 723
DMA RAM address register n (DRAn)........................................................................................................................ 719
DMA SFR address register n (DSAn)......................................................................................................................... 718
E
8-bit A/D conversion result register (ADCRH) .................................................................................................... 389, 397
External interrupt falling edge enable register (EGN0) ............................................................................................... 760
External interrupt falling edge enable register (EGN1) ............................................................................................... 760
External interrupt rising edge enable register (EGP0) ................................................................................................ 760
External interrupt rising edge enable register (EGP1) ................................................................................................ 760
H
Hour count register (HOUR) ....................................................................................................................................... 354
I
IICA control register 0 (IICCTL0) ................................................................................................................................ 584
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011