UPD78F1502AGK-GAK-AX Datasheet, PDF (271/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
6.2 Configuration of Timer Array Unit
The timer array unit includes the following hardware.
Item
Timer/counter
Register
Timer input
Timer output
Control registers
Table 6-1. Configuration of Timer Array Unit
Configuration
Timer counter register mn (TCRmn)
Timer data register mn (TDRmn)
TIpq pin, RxD3 pin (for LIN-bus)
TOpq pins, output controller
<Registers of unit setting block>
• Peripheral enable register 0 (PER0)
• Timer clock select register m (TPSm)
• Timer channel enable status register m (TEm)
• Timer channel start register m (TSm)
• Timer channel stop register m (TTm)
• Timer input select registers 0, 1 (TIS0, TIS1)
• Timer output enable register p (TOEp)
• Timer output register p (TOp)
• Timer output level register p (TOLp)
• Timer output mode register p (TOMp)
<Registers of each channel>
• Timer mode register mn (TMRmn)
• Timer status register pq (TSRpq)
• Input switch control register (ISC) (channel 7 of timer array unit 0 only)
• Noise filter enable registers 1, 2 (NFEN1, NFEN2)
• Port mode registers 1, 3, 5, 8 (PM1, PM3, PM5, PM8)
• Port registers 1, 3, 5, 8 (P1, P3, P5, P8)
Remark
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with
timer I/O pins)
78K0R/LF3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 0, pq = 00 to 04, 07
78K0R/LG3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 0, pq = 00 to 07
78K0R/LH3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 0, 1, pq = 00 to 07, 10 to 13
Figures 6-1 and 6-2 show block diagrams.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011