UPD78F1502AGK-GAK-AX Datasheet, PDF (253/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 5 CLOCK GENERATOR
(b) To stop internal high-speed oscillation clock by setting HIOSTOP to 1
<1> Confirming the CPU clock status (CKC register)
Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high-speed
oscillation clock.
When CLS = 0 and MCS = 0, the internal high-speed oscillation clock is supplied to the CPU, so change
the CPU clock to the high-speed system clock or subsystem clock.
CLS
MCS
CPU Clock Status
0
0
Internal high-speed oscillation clock or 20 MHz internal high-speed
oscillation clock
0
1
High-speed system clock
1
×
Subsystem clock
<2> Stopping the internal high-speed oscillation clock (CSC register)
When HIOSTOP is set to 1, internal high-speed oscillation clock is stopped.
Caution Be sure to confirm that MCS = 1 or CLS = 1 when setting HIOSTOP to 1. In addition, stop
peripheral hardware that is operating on the internal high-speed oscillation clock.
5.6.3 Example of controlling subsystem clock
The subsystem clock can be oscillated by connecting a crystal resonator to the XT1 and XT2 pins.
When the subsystem clock is not used, the XT1/P123 and XT2/P124 pins can be used as input port pins.
Caution The XT1/P123 and XT2/P124 pins are in the input port mode after a reset release.
The following describes examples of setting procedures for the following cases.
(1) When oscillating subsystem clock
(2) When using subsystem clock as CPU clock
(3) When stopping subsystem clock
Caution When the subsystem clock is used as the CPU clock, the subsystem clock is also supplied to the
peripheral hardware (except the real-time counter, timer array unit (when fSUB/2, fSUB/4, the valid edge
of TI0mn input, or the valid edge of INTRTCI is selected as the count clock), clock output/buzzer
output, and watchdog timer). At this time, the operations of the A/D converter and IICA are not
guaranteed. For the operating characteristics of the peripheral hardware, refer to the chapters
describing the various peripheral hardware as well as CHAPTER 31 ELECTRICAL SPECIFICATIONS.
(1) Example of setting procedure when oscillating the subsystem clock
<1> Setting P123/XT1 and P124/XT2 pins (CMC register)
EXCLK
0/1
OSCSEL
0/1
0
OSCSELS
0
0
1
0
AMPHS1 AMPHS0
0/1
0/1
AMPH
0/1
Remark For setting of the P121/X1 and P122/X2 pins, see 5.6.1 Example of controlling high-speed
system clock.
<2> Controlling oscillation of subsystem clock (CSC register)
If XTSTOP is cleared to 0, the XT1 oscillator starts oscillating.
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011