UPD78F1502AGK-GAK-AX Datasheet, PDF (624/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 15 SERIAL INTERFACE IICA
Table 15-4. Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration
During address transmission
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK transfer period after data transmission
When restart condition is detected during data transfer
When stop condition is detected during data transfer
When data is at low level while attempting to generate a restart
condition
When stop condition is detected while attempting to generate a
restart condition
When data is at low level while attempting to generate a stop
condition
When SCL0 is at low level while attempting to generate a
restart condition
Interrupt Request Generation Timing
At falling edge of eighth or ninth clock following byte transfer^{Note 1}
When stop condition is generated (when SPIE = 1)^{Note 2}
At falling edge of eighth or ninth clock following byte transfer^{Note 1}
When stop condition is generated (when SPIE = 1)^{Note 2}
At falling edge of eighth or ninth clock following byte transfer^{Note 1}
Notes 1. When WTIM (bit 3 of IICA control register 0 (IICCTL0)) = 1, an interrupt request occurs at the falling edge of
the ninth clock. When WTIM = 0 and the extension code’s slave address is received, an interrupt request
occurs at the falling edge of the eighth clock.
2. When there is a chance that arbitration will occur, set SPIE = 1 for master device operation.
Remark SPIE: Bit 4 of IICA control register 0 (IICCTL0)
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011