UPD78F1502AGK-GAK-AX Datasheet, PDF (984/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(12/39)
Page
Timer
array unit
ISC: Input switch Be sure to clear bits 5 to 7 to “0”.
p.283 _†
control register
Changing values _{Since the timer operations (operations of TCRpq and TDRpq) are independent of the} p.291 _†
set in registers _{TOpq output circuit and changing the values set in TOp, TOEp, TOLp, and TOMp}
TOp,TOEp,
does not affect the timer operation, the values can be changed during timer
TOLp, and
operation. To output an expected waveform from the TOpq pin by timer operation,
TOMp during
however, set TOp, TOEp, TOLp, and TOMp to the values stated in the register setting
timer operation _{example of each operation.}
When the values set in TOEp, TOLp, and TOMp (except for TOp) are changed close
to the timer interrupt (INTTMpq), the waveform output to the TOpq pin may be
different depending on whether the values are changed immediately before or
immediately after the timer interrupt (INTTMpq) signal generation timing.
Default level of The following figure shows the TOpq pin output level transition when writing has pp.291, _†
TOpq pin and been done in the state of TOEpq = 0 before port output is enabled and TOEpq = 1 is 292
output level after set after changing the default level.
timer operation (a) When operation starts with TOMpq = 0 setting (toggle output)
start
The setting of TOLpq is invalid when TOMpq = 0. When the timer operation
starts after setting the default level, the toggle signal is generated and the output
level of TOpq pin is reversed.
(b) When operation starts with TOMpq = 1 setting (Combination operation mode
(PWM output))
When TOMpq = 1, the active level is determined by TOLpq setting.
Operation of
(a) When TOLpq setting has been changed during timer operation
pp.291, _†
TOpq pin in
When the TOLpq setting has been changed during timer operation, the setting 293
combination
becomes valid at the generation timing of TOpq change condition. Rewriting
operation mode
TOLpq does not change the output level of TOpq.
(TOMpq = 1)
The following figure (Figure 6-30) shows the operation when the value of TOLpq
has been changed during timer operation (TOMpq = 1)
(b) Set/reset timing
To realize 0%/100% output at PWM output, the TOpq pin/TOpq set timing at
master channel timer interrupt (INTTMpq) generation is delayed by 1 count clock
by the slave channel timer interrupt (INTTMqr).
If the set condition and reset condition are generated at the same time, a higher
priority is given to the latter.
Figure 6-31 shows the set/reset operating statuses where the master/slave
channels are set as follows.
Collective
When TOEpq = 1, even if the output by timer interrupt of each timer (INTTMpq)
p.295 _†
manipulation of _{contends with writing to TOpq, output is normally done to TOpq pin.}
TOpq bits
R01UH0004EJ0501 Rev.5.01
968
Jun 20, 2011