UPD78F1502AGK-GAK-AX Datasheet, PDF (326/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 6 TIMER ARRAY UNIT
6.7.3 Operation as frequency divider
The timer array unit can be used as a frequency divider that divides a clock input to the TIpq pin and outputs the result
from TOpq.
The divided clock frequency output from TOpq can be calculated by the following expression.
• When rising edge/falling edge is selected:
Divided clock frequency = Input clock frequency/{(Set value of TDRpq + 1) × 2}
• When both edges are selected:
Divided clock frequency ≅ Input clock frequency/(Set value of TDRpq + 1)
TCRpq operates as a down counter in the interval timer mode.
After the channel start trigger bit (TSpq) is set to 1, TCRpq loads the value of TDRpq when the TIpq valid edge is
detected. If MDpq0 of TMRpq = 0 at this time, INTTMpq is not output and TOpq is not toggled. If MDpq0 of TMRpq = 1,
INTTMpq is output and TOpq is toggled.
After that, TCRpq counts down at the valid edge of TIpq. When TCRpq = 0000H, it toggles TOpq. At the same time,
TCRpq loads the value of TDRpq again, and continues counting.
If detection of both the edges of TIpq is selected, the duty factor error of the input clock affects the divided clock period
of the TOpq output.
The period of the TOpq output clock includes a sampling error of one period of the operation clock.
Clock period of TOpq output = Ideal TOpq output clock period ± Operation clock period (error)
TDRpq can be rewritten at any time. The new value of TDRpq becomes valid during the next count period.
Figure 6-45. Block Diagram of Operation as Frequency Divider
TIpq pin
Edge
detection
Timer counter
(TCRpq)
Output
controller
TOpq pin
TSpq
Data register
(TDRpq)
Remark pq: Unit number + Channel number (only for channels provided with timer I/O pins)
pq = 00, 02 to 04
R01UH0004EJ0501 Rev.5.01
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Jun 20, 2011