UPD78F1502AGK-GAK-AX Datasheet, PDF (924/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (7/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
(e) Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (1/2)
Parameter
Transfer rate
Symbol
Conditions
reception 4.0 V ≤ VDD = EVDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
fCLK = 20 MHz,
fMCK = fCLK
2.7 V ≤ VDD = EVDD < 4.0 V,
2.3 V ≤ Vb < 2.7 V
fCLK = 20 MHz,
fMCK = fCLK
MIN.
TYP.
MAX.
fMCK/6
3.3
Unit
bps
Mbps
fMCK/6
3.3
bps
Mbps
Caution Select the TTL input buffer for RxDq and the N-ch open drain output (VDD tolerance) mode for TxDq by
using the PIMg and POMx registers.
Remarks 1. q: UART number (q = 0 to 3), g: PIM number (g = 1, 7), x: POM number (x = 1, 7, 8)
2. Vb[V]: Communication line voltage
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of the SMRmn register. m: Unit number (m = 0, 1),
n: Channel number (n = 0, 2))
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in UART mode.
4.0 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
2.7 V ≤ VDD = EVDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V: VIH = 2.0 V, VIL = 0.5 V
R01UH0004EJ0501 Rev.5.01
908
Jun 20, 2011