UPD78F1502AGK-GAK-AX Datasheet, PDF (256/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 5 CLOCK GENERATOR
5.6.5 CPU clock status transition diagram
Figure 5-15 shows the CPU clock status transition diagram of this product.
Figure 5-15. CPU Clock Status Transition Diagram
Power ON
(A)
Reset release
Internal high-speed oscillation: Woken up
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation: Stops (input port mode)
DSC oscillation: Stops
VDD < 1.61 V±0.09
VDD ≥ 1.61 V±0.09
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation: Stops (input port mode)
DSC oscillation: Stops
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Cannot be selected by CPU
XT1 oscillation:
Cannot be selected by CPU
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation: Selectable by CPU
DSC oscillation: Selectable by CPU
Notes 2, 3 _(J)
(B)
Note 1
CPU: Operating
with internal high-
speed oscillation
DSC oscillation: Operating
CPU:
Internal high-speed oscillation:
Oscillatable
Operating with
DSC oscillation
X1 oscillation/EXCLK input:
Oscillatable
(D)
CPU:
(C)
XT1 oscillation: Oscillatable
DSC oscillation: Operating
(K)
Operating with
XT1 oscillation
CPU: Operating
with X1 oscillation or
CPU:
EXCLK input
DSC oscillation
→ HALT
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
(G)
Selectable by CPU
(F)
CPU:
XT1 oscillation
→ HALT
XT1 oscillation: Operating
DSC oscillation: Stops
CPU: X1
oscillation/EXCLK
input → HALT
VDD ≥ 1.8 V
(H)
CPU: Internal high-
speed oscillation
→ STOP
(E)
CPU: Internal high-
speed oscillation
→ HALT
(I)
CPU: X1
oscillation/EXCLK
input → STOP
Internal high-speed oscillation:
Oscillatable
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Operating
DSC oscillation: Stops
Internal high-speed
oscillation: Selectable by CPU
X1 oscillation/EXCLK input:
Operating
XT1 oscillation:
Selectable by CPU
DSC oscillation: Stops
Internal high-speed
oscillation: Oscillatable
X1 oscillation/EXCLK input:
Operating
XT1 oscillation: Oscillatable
DSC oscillation: Stops
Internal high-speed
oscillation: Stops
X1 oscillation/EXCLK
input: Stops
XT1 oscillation: Oscillatable
DSC oscillation: Stops
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input:
Oscillatable
XT1 oscillation: Oscillatable
DSC oscillation: Stops
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input:
Stops
XT1 oscillation: Oscillatable
DSC oscillation: Stops
Notes 1.
2.
3.
After reset release, an operation at one of the following operating frequencies is started, because fCLK = fIH/2
has been selected by setting the system clock control register (CKC) to 09H.
• When 1 MHz has been selected by using the option byte: 500 kHz (1 MHz/2)
• When 8 MHz or 20 MHz has been selected by using the option byte: 4 MHz (8 MHz/2)
Specify 20 MHz internal oscillation after checking that VDD is at least 2.7 V.
20 MHz internal oscillation cannot be used if 1 MHz internal oscillation is selected by using the option byte.
Remarks 1. If the low-power-supply detector (LVI) is set to ON by default by the option bytes, the reset will not be
released until the power supply voltage (VDD) exceeds 2.07 V±0.2 V.
After the reset operation, the status will shift to (B) in the above figure.
2. DSC: 20 MHz internal high-speed oscillation clock
R01UH0004EJ0501 Rev.5.01
240
Jun 20, 2011