UPD78F1502AGK-GAK-AX Datasheet, PDF (576/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 14 SERIAL ARRAY UNIT
(2) Processing flow
SSmn “L”
SEmn _{“H”}
SOEmn _{“H”}
SDRmn
SCLr output
SDAr output
SDAr input
Shift
register mn
INTIICr
TSFmn
Figure 14-93. Timing Chart of Data Transmission
Transmit data 1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Shift operation
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
Figure 14-94. Flowchart of Data Transmission
Address field
transmission completed
Starting data transmission
Writing data to SIOr
(SDRmn[7:0])
Transfer end interrupt
No
generated?
Yes
Parity error (ACK error) flag
PEFmn = 1 ?
No
Yes
ACK reception error
No
Data transfer completed?
Yes
Data transmission
completed
Stop condition generation
R01UH0004EJ0501 Rev.5.01
560
Jun 20, 2011