UPD78F1502AGK-GAK-AX Datasheet, PDF (931/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (14/18)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
(g) Communication at different potential (2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
Parameter
SCKp cycle time
SCKp high-/low-level
width
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
tKCY2
4.0 V ≤ VDD ≤ 5.5 V, 13.6 MHz < fMCK
10/fMCK
ns
2.7 V ≤ Vb ≤ 4.0 V 6.8 MHz < fMCK ≤ 13.6 MHz
8/fMCK
ns
fMCK ≤ 6.8 MHz
6/fMCK
ns
2.7 V ≤ VDD < 4.0 V, 18.5 MHz < fMCK
16/fMCK
ns
2.3 V ≤ Vb ≤ 2.7 V 14.8 MHz < fMCK ≤ 18.5 MHz 14/fMCK
ns
11.1 MHz < fMCK ≤ 14.8 MHz 12/fMCK
ns
7.4 MHz < fMCK ≤ 11.1 MHz 10/fMCK
ns
3.7 MHz < fMCK ≤ 7.4 MHz
8/fMCK
ns
fMCK ≤ 3.7 MHz
6/fMCK
ns
tKH2,
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V
fKCY2/2 −
ns
tKL2
20
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
fKCY2/2 −
ns
35
SIp setup time
tSIK2
(to SCKp↑)^{Note 1}
SIp hold time
tKSI2
(from SCKp↑)^{Note 2}
Delay time from SCKp↓ to tKSO2
SOp output^{Note 3}
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
90
1/fMCK + 50
ns
ns
2/fMCK + 120 ns
2/fMCK + 230 ns
Notes 1.
2.
3.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
CSI mode connection diagram (communication at different potential)
<Slave>
SCKp
78K0R/Lx3 _SIp
microcontrollers
SOp
Vb
Rb
SCK
SO User's device
SI
(Caution and Remark are given on the next page.)
R01UH0004EJ0501 Rev.5.01
915
Jun 20, 2011