UPD78F1502AGK-GAK-AX Datasheet, PDF (1002/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
Function
Details of
Function
APPENDIX C LIST OF CAUTIONS
Cautions
(30/39)
Page
Key
interrupt
function
Standby
function
KRM: Key return If any of the KRM0 to KRM7 bits used is set to 1, set bits 0 to 7 (PU70 to PU77) of p.772 _†
mode register the corresponding pull-up resistor register 7 (PU7) to 1.
An interrupt will be generated if the target bit of the KRM register is set while a low p.772 _†
level is being input to the key interrupt input pin. To ignore this interrupt, set the
KRM register after disabling interrupt servicing by using the interrupt mask flag.
Afterward, clear the interrupt request flag and enable interrupt servicing after waiting
for the key interrupt input low-level width (250 ns or more).
The bits not used in the key interrupt mode can be used as normal ports.
p.772 _†
−
The STOP mode can be used only when the CPU is operating on the main system p.773 _†
clock. The STOP mode cannot be set while the CPU operates with the subsystem
clock. The HALT mode can be used when the CPU is operating on either the main
system clock or the subsystem clock.
When shifting to the STOP mode, be sure to stop the peripheral hardware operation p.773 _†
operating with main system clock before executing STOP instruction.
The following sequence is recommended for operating current reduction of the A/D p.773 _†
converter when the standby function is used: First clear bit 7 (ADCS) and bit 0
(ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion
operation, and then execute the STOP instruction.
It can be selected by the option byte whether the internal low-speed oscillator p.773 _†
continues oscillating or stops in the HALT or STOP mode. For details, see
CHAPTER 26 OPTION BYTE.
The STOP instruction cannot be executed when the CPU operates on the 20 MHz p.773 _†
internal high-speed oscillation clock. Be sure to execute the STOP instruction after
shifting to internal high-speed oscillation clock operation.
OSTC:
After the above time has elapsed, the bits are set to 1 in order from MOST8 and p.774 _†
Oscillation
remain 1.
stabilization time _{The oscillation stabilization time counter counts up to the oscillation} p.774 _†
counter status _{stabilization time set by OSTS. If the STOP mode is entered and then}
register
released while the internal high-speed oscillation clock is being used as the
CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
The X1 clock oscillation stabilization wait time does not include the time until clock p.774 _†
oscillation starts (“a” below).
OSTS:
To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS
p.775 _†
Oscillation
before executing the STOP instruction.
stabilization time Setting the oscillation stabilization time to 20 μs or less is prohibited.
p.775 _†
select register _{Before changing the setting of the OSTS register, confirm that the count operation of p.775 †}
the OSTC register is completed.
Do not change the value of the OSTS register during the X1 clock oscillation p.775 _†
stabilization time.
The oscillation stabilization time counter counts up to the oscillation stabilization time p.775 _†
set by OSTS. If the STOP mode is entered and then released while the internal
high-speed oscillation clock is being used as the CPU clock, set the oscillation
stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
R01UH0004EJ0501 Rev.5.01
986
Jun 20, 2011