UPD78F1502AGK-GAK-AX Datasheet, PDF (919/1031 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcontrollers

78K0R/Lx3
CHAPTER 31 ELECTRICAL SPECIFICATIONS
(2) Serial interface: Serial array unit (2/18)
(TA = −40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVss = 0 V)
(b) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCKp cycle time
tKCY1
4.0 V ≤ VDD = EVDD ≤ 5.5 V
200 ^{Note 1}
ns
2.7 V ≤ VDD = EVDD < 4.0 V
300 ^{Note 1}
ns
1.8 V ≤ VDD = EVDD < 2.7 V
600 ^{Note 1}
ns
SCKp high-/low-level width
tKH1,
4.0 V ≤ VDD = EVDD ≤ 5.5 V
tKCY1/2 − 20
ns
tKL1
2.7 V ≤ VDD = EVDD < 4.0 V
tKCY1/2 − 35
ns
1.8 V ≤ VDD = EVDD < 2.7 V
tKCY1/2 − 80
ns
SIp setup time (to SCKp↑) ^{Note 2}
tSIK1
4.0 V ≤ VDD = EVDD ≤ 5.5 V
70
ns
2.7 V ≤ VDD = EVDD < 4.0 V
100
ns
1.8 V ≤ VDD = EVDD < 2.7 V
190
SIp hold time (from SCKp↑) ^{Note 3}
tKSI1
30
Delay time from SCKp↓ to
SOp output ^{Note 4}
tKSO1
C = 30 pF^{Note 5}
ns
ns
40
ns
Notes 1.
2.
3.
4.
5.
The value must also be 4/fCLK or more.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓”
when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for SIp and the normal output mode for SOp and SCKp by using the PIMg
and POMx registers.
Remarks 1. p: CSI number (p = 00, 01, 10, 20), g: PIM number (g = 1, 7), x: POM number (x = 1, 7, 8)
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 2)
R01UH0004EJ0501 Rev.5.01
903
Jun 20, 2011